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k3s7v2000m-tc synch. mrom jedec standard 3.3v power supply lvttl compatible with multiplexed address address: row address: ra 0 ~ ra 12 column address: ca 0 ~ ca 7 (x32): ca 0 ~ ca 8 (x16) switchable organization 4,194,304 x 16(word mode) / 2,097,152 x 32(double word mode) all inputs are sampled at the rising edge of the system clock read performance at memory point of view @33mhz 4-1-1-1 (ras latency=1, cas latency=3) @50mhz 5-1-1-1 (ras latency=1, cas latency=4) @66mhz 5-1-1-1 (ras latency=1, cas latency=4) @83mhz 7-1-1-1 (ras latency=2, cas latency=5) @100mhz 7-1-1-1 (ras latency=2, cas latency=5) t sac : 6ns default mode by user requirement mrs cycle with address key programs -. ras latency(1 & 2) -. cas latency(3 ~ 6) -. burst length : 4, 8 -. burst type : sequential & interleaved dqm for data-out masking package :86tsop2 - 400 general description features 64m-bit (4mx16 /2mx32) synchronous maskrom ordering information part no. max freq. interface package k3s7v2000m-tc10 100mhz lvttl 86tsop2 k3s7v2000m-tc12 83mhz K3S7V2000M-TC15 66mhz k3s7v2000m-tc20 50mhz k3s7v2000m-tc30 33mhz the k3s7v2000m-tc is a synchronous high bandwidth mask programmable rom fabricated with samsung s high perfor- mance cmos process technology and is organized either as 4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double word mode) depending on polarity of word pin.(see pin func- tion description). synchronous design allows precise cycle con- trol, with the use of system clock, i/o transactions are possible on every clock cycle. range of operating frequencies, program- mable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. functional block diagram * samsung electronics reserves the right to change products or specification without notice. timing register 4m x 16 /2m x 32 s e n s e a m p . column decoder latency & burst length programming register a d d r e s s r e g i s t e r r o w b u f f e r r o w d e c o d e r c o l . b u f f e r l r a s lcke lras lmr clk cke mr ras cas cs clk add lcas output buffer . . . q0 q16 q15 q31 cell array dqm
k3s7v2000m-tc synch. mrom pin configuration (top view) 86tsopii - 400 (0.5 mm pin pitch) v dd q0 v dd q q16 q1 vssq q17 q2 v dd q q18 q3 q19 mr# v dd dqm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 86 85 84 83 82 81 80 79 78 vssq nc cas# ras# cs# a12 a11 a10 a0 word# a1 a2 nc v dd nc q4 vssq q20 q5 v dd q q21 q6 vssq q22 q7 v dd q q23 v dd vss q31 vssq q15 q30 v dd q q14 q29 vssq q13 q28 q12 nc vss nc v dd q nc nc clk cke a8 a7 a6 a5 a4 a3 nc vss nc q27 v dd q q11 q26 vssq q10 q25 v dd q q9 q24 vssq q8 vss a9
k3s7v2000m-tc synch. mrom pin function description note1. v dd and v dd q is same voltage. pin name input function clk system clock active on the rising edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk and cke. cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disables input buffers for power down in standby mode. a 0 ~ a 12 address row / column addresses are multiplexed on the same pins. row address: ra 0 ~ ra 12 , column address: ca 0 ~ ca 7 (x32): ca 0 ~ ca 8 (x16) ras row address strobe latches row addresses on the rising edge of the clk with ras low. enables row access cas column address strobe latches column addresses on the rising edge of the clk with cas low. enables column access. mr mode register set enables mode register set with mr low. (simultaneously cs , ras and cas are low) q 0 ~ q 31 data output v dd /v ss power supply/ground power and ground for the input buffers and the core logic. v dd q /v ss q data output power/ ground power and ground for the output buffers. word x32/x16 mode selection double word mode/word mode, depending on polarity of word pin. should be set before cas enabling. dqm data-out masking it works similar to oe during read operation. n.c no connection this pin is recommended to be left no connection on the device.
k3s7v2000m-tc synch. mrom absolute maximum ratings note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. parameter symbol min max unit voltage on v dd relative to vss v dd , v dd q -0.5 4.6 v voltage on any pin relative to vss v in , v out -0.5 v dd + 0.5 4.6 v operating temperature t a 0 70 c storage temperature t stg -55 125 c short circuit current i os - 50 ma power dissipation p d - 1 w dc operating conditions recommended operating conditions(voltage referenced to v ss , t a =0 to 70 c) parameter symbol min typ max unit supply voltage v dd , v dd q 3.0 3.3 3.6 v supply voltage(ground) v ss, v ss q 0 0 0 v dc characteristics note : 1. v ih (max)=4.6v for pulse width 10ns acceptable, pulse width measured at 50% of pulse amplitude. 2. v il (min)=-1.5v for pulse width 10ns acceptable, pulse width measured at 50% of pulse amplitude. 3. the condition is the same as self refresh mode of sdram, that is, in this case cs , ras , cas have to be set to low, mr has to be set to high. parameter symbol min max unit test condition standby current ( note3) i cc3p - 150 ua cke v il (max), t cc =min i cc3ps - 150 ua cke=0, t cc =min active standby current i cc3n - 50 ma cs 3 v ih (min), t cc =min, all outputs open burst mode operating current i cc4 - 100 ma t cc =min, all outputs open input leakage current i il -10 10 ua 0v v in v dd + 0.3v pins not under test=0v output leakage current (dout disabled) i ol -10 10 ua (0v v out v dd max) q# in high-z input high voltage, all inputs v ih 2.0 v dd + 0.3 v (note1) input low voltage, all inputs v il -0.3 0.8 v (note2) output high voltage level (logic 1) v oh 2.4 - v i oh =-2ma output low voltage level (logic 0) v ol - 0.4 v i ol =2ma
k3s7v2000m-tc synch. mrom ac operating test conditions (t a = 0 to 70 c, v dd = 3.3v 0.3v, unless otherwise noted.) note : if clk transition time is longer than 1ns, timing parameters should be compensated. add [(tr+tf)/2-1]ns for transition ti me longer than 1ns. transi- tion time is measured between v il (max) and v ih (min). parameter value timing reference levels of input/output signals 1.4v input signal levels v ih /v il =2.4v/0.4v transition time (rise & fall) of input signals tr/tf=1ns/1ns output load lvttl 3.3v 1200 w 870 w output 50pf v oh (dc)=2.4v, i oh =-2ma v ol (dc)=0.4v, i ol =2ma vtt=1.4v 50 w output 50pf z 0 =50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit (ac operating conditions unless otherwise noted) note : 1. these t rc values are for bl=8. for bl=4, t rc =6 clks for up to 100mhz, t rc =6 clks for up to 83mhz, t rc =4 clks for up to 66mhz, t rc =4 clks for up to 50mhz, and t rc =3 clks for up to 33mhz. ras latency increase means, a simultaneous t rc increase in the same number of cycles. ( if ras latency is 3 clks, t rc is 12 clks for bl=8.) refer to attached technical note for gapless operation. 2. these t vcvc values are for bl=8. for bl=4, t vcvc =4clks for up to 100mhz, t vcvc =4clks for up to 83mhz, t vcvc =3clks for up to 66mhz, t vcvc =3clks for up to 50mhz, and t vcvc =2clks for up to 33mhz. refer to attached technical note for gapless operation. parameter symbol up to 100mhz up to 83mhz up to 66mhz up to 50 mhz unit notes min max min max min max min max clk cycle time t cc 10 12 15 - 20 - ns clk to valid output delay t sac - 6 - 6 - 6 - 6 ns data output hold time t oh 2 - 2 - 2 - 2 - ns clk high pulse width t ch 3 - 3.5 - 4 - 6.5 - ns clk low pulse width t cl 3 - 3.5 - 4 - 6.5 - ns row-active to row-active t rc 10 - 10 - 8 - 8 - clks 1 input setup time t ss 2 - 3 - 4 - 4 - ns input hold time t sh 1 - 1 - 2 - 2 - ns clk to output in low-z t slz 0 - 0 - 0 - 0 - ns clk to output in high-z t shz - 7 - 8 - 10 - 15 ns transition time t t 0.1 10 0.1 10 0.1 10 0.1 10 ns valid cas enable to valid cas enable t vcvc 8 - 8 - 7 - 7 - clks 2 operating ac parameters
k3s7v2000m-tc synch. mrom capacitance (t a =25 c, f=1mhz) parameter symbol min max unit input capacitance c in - 5 pf output capacitance c out - 7 pf function truth table (v=valid, x=don 't care, h=logic high, l=logic low) abbreviations (ra: row address, ca: column address, nop: no operation command, dwm: double word mode, wm: word mode) notes : 1. a 0 ~ a 6 : program keys (@mrs). after power up, mode register set, can be set before issuing other input command. after the mode register set com- mand is completed, no new commands can be issued for 3 clk cycles, and cs or mr state must be defined "h" within 3 clk cycles. refer to the mode register field table 2. in the case cke is low, two standby modes are possible. those are stand-by mode in power-down. power down: cke="l" (at all the parts except the range of row active, read & data out) clock suspend: cke="l" (at the range of row active, read & data out) 3. dqm sampled at rising edge of a clk makes a hi-z state the data-out state, delayed by 2clk cycles. 4. precharge command on synch.dram can be used for burst stop operation during burst read operation only. 5. mode selection control is decided simultaneously with column access start, and according to the polarity of word pin, "h" state is dwm, "l" state is wm. command cken -1 cken cs ras cas mr dqm add. word notes register mode register set h x l l l l x code x 1 row active row access& latch row access & latch h x l l h h x ra x read column access & latch h x l h l h x ca x burst stop (burst stop on synch.dram) h x l h h l x x x (precharge on synch.dram) h x l l h l x x x power down & clock suspend two standby mode entry h l x x x x x x x 2 exit l h x x x x x x x dqm h x v x 3 illegal (write on synch.dram) h x l h l l x ca x (refresh on synch.dram) h x l l l h x x x no operation command h x h x x x x x x 4 h x l h h h x x x organization control h x l h l h x ca h 5 l
k3s7v2000m-tc synch. mrom ras latency a 6 length 0 1 1 2 register programmed with mrs address a 6 a 5 a 4 a 3 a 2 a 1 a 0 function ras latency cas latency burst type burst length burst length a 1 a 0 length 0 0 reserved 0 1 4 1 0 8 1 1 reserved burst type a 2 type 0 sequential 1 interleave cas latency a 5 a 4 a 3 length 0 0 0 reserved 0 0 1 reserved 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 reserved 1 1 1 reserved notes : -. after power up, when user wants to change mode register set, user must exit from power down mode and start mode register set before entering normal operation mode. mode register field table to program modes (3) each address is arranged as follows for x32 operation , for x16 operation, when ca8 is set to low, data belonging to 0~15th registers are output to q0~q15 pins, and when ca8 is set to high, data belongin g to16~31th registers are output to q0~ q15 pins. address register ar20 ar19 ar18 ... ar9 ar8 ar7 ar6 ... ar3 ar2 ar1 ar0 address ra12 ra11 ra10 ... ra1 ra0 ca7 ca6 ... ca3 ca2 ca1 ca0 (1) word = "h" : x32 organization note : column address msb (at x32 organization) (x=don 't care) function a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 row address ra 0 ra 1 ra 2 ra 3 ra 4 ra 5 ra 6 ra 7 ra 8 ra 9 ra 10 ra 11 ra 12 column address ca 0 ca 1 ca 2 ca 3 ca 4 ca 5 ca 6 ca 7 note x x x x x (2) word ="l" : x16 organization note : column address msb (at x16 organization) (x=don 't care) function a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 row address ra 0 ra 1 ra 2 ra 3 ra 4 ra 5 ra 6 ra 7 ra 8 ra 9 ra 10 ra 11 ra 12 column address ca 0 ca 1 ca 2 ca 3 ca 4 ca 5 ca 6 ca 7 ca 8 note x x x x addressing map * initial address - bl=4(ca0,ca1) - bl=8(ca0,ca1,ca2) bl=8 bl=4 msb lsb
k3s7v2000m-tc synch. mrom x32 operation (double word mode) column address d15 ~ d0 (hexadecimal) d31 ~ d16 (hexadecimal) ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 0 0 0 0 0 0 0 0 a a a a 0 0 0 0 0 0 0 0 0 0 0 1 b b b b 1 1 1 1 0 0 0 0 0 0 1 0 c c c c 2 2 2 2 0 0 0 0 0 0 1 1 d d d d 3 3 3 3 0 0 0 0 0 1 0 0 e e e e 4 4 4 4 0 0 0 0 0 1 0 1 f f f f 5 5 5 5 x16 operation (word mode) column address data out (hexadecimal) comment ca8 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 0 0 0 0 0 0 0 0 0 a a a a d15 ~ d0 0 0 0 0 0 0 0 0 1 b b b b d15 ~ d0 0 0 0 0 0 0 0 1 0 c c c c d15 ~ d0 0 0 0 0 0 0 0 1 1 d d d d d15 ~ d0 0 0 0 0 0 0 1 0 0 e e e e d15 ~ d0 0 0 0 0 0 0 1 0 1 f f f f d15 ~ d0 : 1 0 0 0 0 0 0 0 0 0 0 0 0 d31 ~ d16 1 0 0 0 0 0 0 0 1 1 1 1 1 d31 ~ d16 1 0 0 0 0 0 0 1 0 2 2 2 2 d31 ~ d16 burst sequence(burst length = 4) initial address sequential interleave a1 a0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 burst sequence(burst length = 8) initial address sequential interleave a2 a1 a0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0
k3s7v2000m-tc synch. mrom clock (clk) the clock input is used as a reference for smrom operation. a square wave signal(clk) must be applied externally at cycle time t cc. all operations are synchronized to the rising edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high, all inputs are assumed to be in valid state (low or high) for the duration of set-up and hold ti me around the positive edge of the clock for proper functionality and i cc specifications. clock enable (cke) the clock enable(cke) gates the clock into the smrom and is asserted high during all cycles, except for power down, stand-by and clock suspend mode. if cke goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is sus- pended from the next clock cycle and the state of output and burst address is frozen for as long as the cke remains low. all oth er inputs are ignored from the next clock cycle after cke goes low. the smrom remains in the power down mode ignoring other inputs for as long as cke remains low. the power down exit is synchronous as the internal clock is suspended. when cke goes high at least "1 clk + t ss " before the rising edge of the clock, then the smrom becomes active from the same clock edge accepting all the input commands. nop and device deselect when ras , cas and mr are high, the smrom performs no operation (nop). nop does not initiate any new operation. device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas , mr and all the address inputs are ignored. in addition, entering a mode register set command in the middle of a normal operation, results i n an illegal state in smrom. power-up the following power-up sequence is recommended. 1. apply power and start clock, attempt to maintain mr , cke and dqm inputs to pull them high and the other pins are nop condition at the inputs before or along with v dd (and v dd q) supply. 2. maintain stable power, stable clock and nop input condition for a minimum of 20us. 3. when user wants to change the default mode register set values, perform a mode register set cycle to program the ras latency, cas latency, burst length and burst type. 4. at the end of three clock cycles after the mode register set cycle, the device is ready for operation. when the above sequenc e is used for power-up, all outputs will be in high impedance state. the high impedance of outputs is not guaranteed in any other power-up sequence. mode selection control mode selection control is decided simultaneously with column access, and according to word pin voltage level. high level signifies double word mode(x32) and low level signifies word mode(x16). address decoding the address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select pins and latched by externally applying two commands. the first command, ras asserted low, latches the row address into the device. a second command, cas asserted low, subsequently latches the column address. device operations
k3s7v2000m-tc synch. mrom mode register set (mrs) the mode register stores the data for controlling the various operating modes of smrom. it programs the ras latency, cas latency , burst length, burst type. on power-up, the mode register is set to the default value defined by the user requirement. when and i f the user wants to change its values, the user must exit from power down mode and start mode register set before entering normal oper - ation mode. the mode register is reprogrammed by asserting low on cs , ras , cas and mr (the smrom should be in active mode with cke already high prior to writing the mode register). the state of address pins a 0 ~ a 7 in the same cycle as cs , ras , cas and mr going low is the data written in the mode register. three clock cycles are required to complete the program in the mode registe r, therefore after mode register set command is completed, no new commands can be issued for 3 clock cycles and cs or mr must be fixed to high within 3 clock cycles. the mode register is divided into various fields depending on functionality. the burst leng th field uses a 0 ~ a 1 , burst type uses a 2 , cas latency (read latency from column address) uses a 3 ~ a 5, ras latency uses a 6 ( ras to cas delay). refer to the table for specific codes for various burst length, burst type, cas latencies and ras latencies. latency there are latencies between the issuance of a row active command and when data is available on the i/o buffers. the ras to cas delay is defined as the ras latency. the cas to data out delay is the cas latency. the cas and ras latencies are programmable through the mode register. ras latencies of 1 and 2, and cas latencies of 3 through 6 are supported. it is understood that some ras and cas latency values are reserved for future use, and may not be available in the first generation for smrom. the followin gs are the supported minimum values in the first generation. ras latency=2, and cas latency=5 for 100mhz operation, and ras latency=2, and cas latency=5 for 83mhz operation, and ras latency=1, and cas latency=4 for 66mhz operation, and ras latency=1, and cas latenecy=4 for 50mhz operation, and ras latency=1, and cas latenecy=3 for 33mhz operation. dqm operation the dqm is used to mask output operations when a complete burst read is not required. it works similar to oe during a read opera- tion. the read latency is two cycles from dqm, which means dqm masking occurs two cycles later in the read cycle. dqm operation is synchronous with the clock. the masking occurs for a complete cycle. (also refer to the dqm timing diagram) burst read the burst read command is used to access a burst of data on consecutive clock cycles from an active row state. the burst read co m- mand is issued by asserting low cs and cas with mr being high on the rising edge of the clock. the first output appears in cas latency number of clock cycles after the issuance of the burst read command. the burst length, burst sequence and latency from t he burst read command are determined by the mode register which is already programmed. burst read can be initiated on any column address of the active row. the output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep the data output gapless. the burst read can be terminated by issuing another burst read. device operations
k3s7v2000m-tc synch. mrom d 0 internal clk internal clk cke internal clk note : 1. after mode register set command is completed, no new commands can be issued for 3 clock cycles, and mr or cs should be fixed "h" within a minimum of 3 clock cycles. basic feature and function descriptions 1. mrs mode register set clk cmd mrs act note 1 3clk 2. clock suspend clock suspended during burst read (bl=4) masked by cke q 0 q 1 q 2 q 3 suspended dout clk cmd rd cke data 3. clock suspend exit & power down exit 1) clock suspend exit clk cke cmd rd 2) power down exit clk cmd nop act t ss t ss : this command do not be activated.
k3s7v2000m-tc synch. mrom q 0 q 1 q 3 q 0 q 2 q 3 q 1 q 2 q 3 masked by dqm q 0 d 1 q 1 q 8 q 3 q 0 q 7 q 8 q 2 q 6 q 7 q 1 *note : 1. dqm makes data out hi-z after 2clks which should masked by cke " l" q 7 q 6 q 5 4. dqm operation clk cmd dqm data(cl2) data(cl3) data(cl4) rd clk cmd dqm cke rd 1) read mask (bl=4) 2) dqm with clock suspended (bl=8) hi-z hi-z hi-z q 5 q 4 q 3 hi-z hi-z hi-z hi-z hi-z hi-z dqm to data-out mask = 2clks hi-z hi-z hi-z note 1 data(cl2) data(cl3) data(cl4)
k3s7v2000m-tc synch. mrom read cycle i : normal @ras latency=2, cas latency=5, burst length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss t sh cke cs ras cas addr data t ch t cc t cl high t sh t ss t shz t sac t oh qa0 qa1 qa2 qa3 cab rab *note: 1. when the burst length is 4 at 100mhz, t rc is equal to 6 clock cycles. ras latency mr *note 1 t rc =6 clocks at bl=4 row active read row active read : don 't care t ss t sh qb0 qb1 qb2 qb3 caa raa clk t rc
k3s7v2000m-tc synch. mrom read cycle ii : consecutive column access @ras latency = 2, cas latency=5, bl = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss t sh t ss t sh cke cs ras cas addr data t ch t cc t cl high t sh t ss caa raa t shz t sac t oh qb1 qb2 qb3 cab note: when column access is initiated beyond t vcvc, 1. at bl=4, caa access read is completed, cab access read begins. qb0 ras latency t vcvc =4 clocks at bl=4 burst length=4 qa1 qa2 qa3 qa0 mr row active read read : don 't care clk *note 1
k3s7v2000m-tc synch. mrom read cycle iii : clock suspend @ras latency = 2, cas latency=5, burst length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss t sh cke cs ras cas addr data t ch t cc t sh t ss caa raa note : 1. from next clock after cke goes low, clock suspension begins. 2. for clock suspension, data output state is held & maintained. ras latency t vcvc = 4 clocks at bl=4 *note 2 burst length=4 qa2 qa3 *note 1 mr row active read clock suspend resume : don 't care qa1 clk internal clk t cl qa0
k3s7v2000m-tc synch. mrom read interrupted by precharge command & burst read stop cycle @burst length=8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *note : 1. the burst stop command is valid at every page burst length. the data bus goes to high-z after the cas latency from the burst stop command is issued. 2. the interval between read command (column address presented) and burst stop command is 1 cycle(min). high cl=3 addr cas ras cs cke clk mr dqm qa0 qa1 qa2 qa4 qb0 qb1 qb2 qb3 qb4 qb5 raa caa cab row active precharge burst stop read read : don 't care note1 cl=2 data qa0 qa1 qa2 qa4 qb0 qb1 qb2 qb3 qb4 qb5 qa3 qa3 *note1, 2 note1 note2 note2
k3s7v2000m-tc synch. mrom power down & clock suspend cycle : @ras latency = 2, cas latency=5, burst length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas addr data power down read clock suspend caa raa qa1 qa2 qa0 mr qa3 row active (high) data hi-z state clk (internal) nop power-down clock suspend entry entry power-down exit clock suspend exit note : 1. from next clock after cke goes low, clock suspend and power down begins. 2. after power down exit, nop should be issued and new command can be issued after 1clock. : don 't care t ss t sh *note 2 *note 1 t ss *note 1
k3s7v2000m-tc synch. mrom mode register set: @ras latency = 2, cas latency=5, burst length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t ss t sh cke cs ras cas addr data mr t cc t cl high code raa note : 1. after the mode register set is completed, no new commands can be issued for 3clk cycles. 2. after power up, necessarily mode register set should be completed at least one time and cs or mr must be fixed "h" within 3clock cycles, and when user wants to change mode register set, user must exit from power down mode and start mode reg- ister set before chip enters normal operation mode. ras latency data hi-z state mrs row active : don 't care caa qa0 qa1 qa2 qa3 clk t ch
k3s7v2000m-tc synch. mrom function truth table * : after the power up, when user wants to change mr set, user must exit from power down mode and start mr set before chip ent ers normal operation mode. current state input signal next state operation cke cs ras cas mr add. after power up* l x x x x x -. power down h l l h h ra -. row active ; latch ra h l l l l code -. mode register set row active h l l h h ra -. if consecutive row access is issued within t rcmin. without cas enabling, only the final ra is valid. h l h l h ca -. begin read ; latch ca h l l l l code illegal * l x x x x x -. clock suspend read h l l h h ra -. row access in read state, within the trc, previous read is ignored and new row is activated. beyond the trc, previous read is completed and new read begins. h l h l h ca -. consecutive column access, within the t vcvc , only the final ca is valid and the previous burst read is ignored. beyond the t vcvc , the previous read is completed and new read begins. h l l h l x -. nop (after burst read) / read interrupt h l h h l x -. nop (after burst read) / read interrupt h l l l l code illegal * l x x x x x -. clock suspend / power down any state l l l l h x -. low power consumption mode any state h l h h h x nop any state h l l l h x illegal h l h l l ca illegal
k3s7v2000m-tc synch. mrom k3s7v2000m-tc12 burst length ras latency cas latency trcmin. tvcvcmin. 4 2 5 6 4* 6 7 5 8 2 5 10 8* 6 11 9 technical notes ( unit : number of clock ) 1. frequency vs. ac parameter relationship table k3s7v2000m-tc10 burst length ras latency cas latency trcmin. tvcvcmin. 4 2 5 6 4* 6 7 5 8 2 5 10 8* 6 11 9 ( unit : number of clock ) K3S7V2000M-TC15 burst length ras latency cas latency trcmin. tvcvcmin. 4 1 4 4* 3/ 4* 5 5 4* 6 6 5 2 4 5 3/ 4* 5 6 4* 6 7 5 8 1 4 8* 7/ 8* 5 9 8* 6 10 9 2 4 9 7/ 8* 5 10 8* 6 11 9 ( unit : number of clock )
k3s7v2000m-tc synch. mrom k3s7v2000m-tc20 burst length ras latency cas latency trcmin. tvcvcmin. 4 1 4 4* 3/ 4* 5 5 4* 6 6 5 2 4 5 3/ 4* 5 6 4* 6 7 5 8 1 4 8* 7/ 8* 5 9 8* 6 10 9 2 4 9 7/ 8* 5 10 8* 6 11 9 ( unit : number of clock ) k3s7v2000m-tc30 burst length ras latency cas latency trcmin. tvcvcmin. 4 1 3 3/ 4* 2/ 4* 4 4* 3/ 4* 5 5 4* 6 6 5 2 3 4* 2 /4* 4 5 3 /4* 5 6 4* 6 7 5 8 1 3 7/ 8* 6/ 8* 4 8* 7/ 8* 5 9 8* 6 10 9 2 3 8* 6 /8* 4 9 7 /8* 5 10 8* 6 11 9 ( unit : number of clock ) note : above tables are not specification values, rather actual values. there are no gapless operations for cas latency 6. * : minimum clocks for gapless operation.
k3s7v2000m-tc synch. mrom rd pre q 0 q 0 q 1 q 0 q 1 rd q 0 q 1 q 0 q 1 q 0 q 1 q 1 3. read interrupt operation by issuing the precharge or burst stop command clk cmd clk cmd qb 1 qb 2 rd qb 3 rd a b qb 0 qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 note 2 data(cl2) data(cl3) data(cl4) *note : 1. by " interrupt", it is meant to stop burst read by external command before the end of burst. by "cas interrupt", to stop burst read by cas access. 2. cas to cas delay. (=1clk) 2. cas interrupt read interrupted by read (bl=4) note 1 clk cmd add case i ) issued read interrupt command during burst read operation period. rd pre q 0 q 0 q 0 note 2 rd stop q 0 q 0 q 0 clk cmd clk cmd case ii ) issued read interrupt command between read command and data out. *note : 1. the data bus goes to high-z after cas latency from the burst stop (or precharge) command. 2. valid output data will last up to cl-1 clock cycle from pre command. note 2 note 1 note 1 technical notes (continuous) data(cl2) data(cl3) data(cl4) data(cl2) data(cl3) data(cl4) data(cl2) data(cl3) data(cl4) data(cl2) data(cl3) data(cl4) stop
k3s7v2000m-tc synch. mrom rda 4. read cycle depending on t rc @ rl = 1, cl = 4, bl = 4 ; 66mhz trc(min)=4 act tcc=15ns rdb act rdb qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 qa 1 qa 2 qa 0 qa 3 qa 1 qa 2 qa 0 qa 3 high-z case i ) rdb act case ii ) case iii ) act qb 1 qb 2 qb 3 qb 0 clk cmd case i ) case ii ) case iii ) @ rl = 2, cl = 5, bl = 4 ; 83mhz @ rl = 2, cl = 5, bl = 4 ; 100mhz rda trc(min)=6 act tcc=12ns rdb act rdb qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 qa 1 qa 2 qa 0 qa 3 qa 1 qa 2 qa 0 qa 3 high-z case i ) rdb act case ii ) case iii ) act qb 1 qb 2 qb 3 qb 0 clk cmd case i ) case ii ) case iii ) rda trc(min)=6 act tcc=10ns rdb act rdb qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 qa 1 qa 2 qa 0 qa 3 qa 1 qa 2 qa 0 qa 3 high-z case i ) rdb act case ii ) case iii ) act qb 1 qb 2 qb 3 qb 0 clk cmd case i ) case ii ) case iii ) (gapless operation)
k3s7v2000m-tc synch. mrom @ rl = 1, cl = 4, bl = 4 ; 50mhz trc(min)=4 act tcc=20ns act qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 qa 1 qa 2 qa 0 qa 3 qa 1 qa 2 qa 0 qa 3 case i ) act case ii) case iii) act @ rl = 1, cl = 3, bl = 4 ; 33mhz trc(min)=3 act tcc=30ns act qb 1 qb 2 qb 3 qb 0 qb 2 qb 3 qb 1 qa 1 qa 0 qa 2 qa 1 qa 2 qa 0 qa 3 case i) act case ii) case iii) act qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 : invalid data clk cmd case i ) case ii ) case iii ) clk cmd case i ) case ii ) case iii ) rda rdb rdb rdb rda rdb rdb rdb (gapless operation) (gapless operation) : invalid data
k3s7v2000m-tc synch. mrom 5. read cycle depending on tvcvc @ rl = 1, cl = 4, bl = 4 ; 66mhz tvcvc=3 act qb 1 qb 2 qb 3 qb 0 case i) case ii) case iii) clk cmd case i ) case ii ) case iii ) qb 1 qb 2 qb 3 qb 1 qb 2 qb 3 qb 0 qa 0 qa 1 qa 0 rda rdb rdb rdb qa 1 (gapless operation) qa 3 qa 2 tcc=15ns @ rl = 2, cl = 5, bl = 4 ; 100mhz @ rl = 2, cl = 5, bl = 4 ; 83mhz tvcvc=4 act qb 1 qb 2 qb 3 qb 0 case i) case ii) case iii) clk cmd case i ) case ii ) case iii ) qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 qa 0 qa 1 qa 0 rda rdb rdb rdb qa 2 qa 3 qa 1 (gapless operation) qa 3 qa 2 tcc=12ns tvcvc=4 act qb 1 qb 2 qb 3 qb 0 case i) case ii) case iii) clk cmd case i ) case ii ) case iii ) qb 1 qb 2 qb 3 qb 0 qb 1 qb 2 qb 3 qb 0 qa 0 qa 1 qa 0 rda rdb rdb rdb qa 2 qa 3 qa 1 (gapless operation) qa 3 qa 2 tcc=10ns : invalid data : invalid data : invalid data qb 2
k3s7v2000m-tc synch. mrom @ rl = 1, cl = 4, bl = 4 ; 50mhz tvcvc=3 act qb 1 qb 2 qb 3 qb 0 case i) case ii) case iii) clk cmd case i ) case ii ) case iii ) qb 1 qb 2 qb 3 qb 1 qb 2 qb 3 qb 0 qa 0 qa 1 qa 0 @ rl = 1, cl = 3, bl = 4 ; 33mhz tvcvc=2 act qb 1 qb 2 qb 3 qb 0 case i) case ii) case iii) clk cmd case i ) case ii ) case iii ) qb 1 qb 2 qb 3 qb 1 qb 2 qb 3 qa 0 qa 1 qa 0 rda rdb rdb rdb rda rdb rdb rdb qa 3 qa 2 (gapless operation) : invalid data : invalid data qa 2 qa 1 qa 2 qa 1 tcc=20ns tcc=30ns
k3s7v2000m-tc synch. mrom 6. read cycle depending on t vcvc and t rc @ rl = 1, cl = 4, bl = 4 ; 50mhz (gapless operation) tvcvc=4 act clk cmd read out qc 0 qc 1 qa 0 @ rl = 1, cl = 4, bl = 4 ; 50mhz clk @ rl = 1, cl = 4, bl = 4 ; 50mhz clk rda rdb qa 2 qa 1 : invalid data act rdc tcc=20ns tcc=20ns tcc=20ns qc 2 : invalid data cmd read out qc 0 qa 0 qa 2 qa 1 qc 2 qa 3 qc 3 act cmd read out qa 0 rda rdb qa 2 qa 1 qb 0 qa 3 qb 1 qb 2 tvcvc=4 tvcvc=4 act rda rdb act rdc qb 3 act rdc qc 1 rdf rdd act rde qc 0 qc 2 qc 1 qd 0 qc 3 qd 1 qd 2 rdd act rde rdf qe 0 rdd act rde qe 0 qe 2 qe 1

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